9.1.15. MIPI CCS camera sensor driver¶
The MIPI CCS camera sensor driver is a generic driver for MIPI CCS compliant camera sensors. It exposes three sub-devices representing the pixel array, the binner and the scaler.
As the capabilities of individual devices vary, the driver exposes interfaces based on the capabilities that exist in hardware.
9.1.15.1. Pixel Array sub-device¶
The pixel array sub-device represents the camera sensor’s pixel matrix, as well
as analogue crop functionality present in many compliant devices. The analogue
crop is configured using the V4L2_SEL_TGT_CROP
on the source pad (0) of the
entity. The size of the pixel matrix can be obtained by getting the
V4L2_SEL_TGT_NATIVE_SIZE
target.
9.1.15.2. Binner¶
The binner sub-device represents the binning functionality on the sensor. For
that purpose, selection target V4L2_SEL_TGT_COMPOSE
is supported on the
sink pad (0).
Additionally, if a device has no scaler or digital crop functionality, the source pad (1) expses another digital crop selection rectangle that can only crop at the end of the lines and frames.
9.1.15.3. Scaler¶
The scaler sub-device represents the digital crop and scaling functionality of
the sensor. The V4L2 selection target V4L2_SEL_TGT_CROP
is used to
configure the digital crop on the sink pad (0) when digital crop is supported.
Scaling is configured using selection target V4L2_SEL_TGT_COMPOSE
on the
sink pad (0) as well.
Additionally, if the scaler sub-device exists, its source pad (1) exposes another digital crop selection rectangle that can only crop at the end of the lines and frames.
9.1.15.4. Digital and analogue crop¶
Digital crop functionality is referred to as cropping that effectively works by dropping some data on the floor. Analogue crop, on the other hand, means that the cropped information is never retrieved. In case of camera sensors, the analogue data is never read from the pixel matrix that are outside the configured selection rectangle that designates crop. The difference has an effect in device timing and likely also in power consumption.
9.1.15.5. Register definition generator¶
The ccs-regs.asc file contains MIPI CCS register definitions that are used to produce C source code files for definitions that can be better used by programs written in C language. As there are many dependencies between the produced files, please do not modify them manually as it’s error-prone and in vain, but instead change the script producing them.
9.1.15.5.1. Usage¶
Conventionally the script is called this way to update the CCS driver definitions:
$ Documentation/driver-api/media/drivers/ccs/mk-ccs-regs -k \
-e drivers/media/i2c/ccs/ccs-regs.h \
-L drivers/media/i2c/ccs/ccs-limits.h \
-l drivers/media/i2c/ccs/ccs-limits.c \
-c Documentation/driver-api/media/drivers/ccs/ccs-regs.asc
9.1.16. CCS PLL calculator¶
The CCS PLL calculator is used to compute the PLL configuration, given sensor’s capabilities as well as board configuration and user specified configuration. As the configuration space that encompasses all these configurations is vast, the PLL calculator isn’t entirely trivial. Yet it is relatively simple to use for a driver.
The PLL model implemented by the PLL calculator corresponds to MIPI CCS 1.1.
-
struct
ccs_pll_branch_fr
¶ CCS PLL configuration (front)
Definition
struct ccs_pll_branch_fr {
u16 pre_pll_clk_div;
u16 pll_multiplier;
u32 pll_ip_clk_freq_hz;
u32 pll_op_clk_freq_hz;
};
Members
pre_pll_clk_div
- Pre-PLL clock divisor
pll_multiplier
- PLL multiplier
pll_ip_clk_freq_hz
- PLL input clock frequency
pll_op_clk_freq_hz
- PLL output clock frequency
Description
A single branch front-end of the CCS PLL tree.
-
struct
ccs_pll_branch_bk
¶ CCS PLL configuration (back)
Definition
struct ccs_pll_branch_bk {
u16 sys_clk_div;
u16 pix_clk_div;
u32 sys_clk_freq_hz;
u32 pix_clk_freq_hz;
};
Members
sys_clk_div
- System clock divider
pix_clk_div
- Pixel clock divider
sys_clk_freq_hz
- System clock frequency
pix_clk_freq_hz
- Pixel clock frequency
Description
A single branch back-end of the CCS PLL tree.
-
struct
ccs_pll
¶ Full CCS PLL configuration
Definition
struct ccs_pll {
u8 bus_type;
u8 op_lanes;
u8 vt_lanes;
struct {
u8 lanes;
} csi2;
u8 binning_horizontal;
u8 binning_vertical;
u8 scale_m;
u8 scale_n;
u8 bits_per_pixel;
u8 op_bits_per_lane;
u16 flags;
u32 link_freq;
u32 ext_clk_freq_hz;
struct ccs_pll_branch_fr vt_fr;
struct ccs_pll_branch_bk vt_bk;
struct ccs_pll_branch_fr op_fr;
struct ccs_pll_branch_bk op_bk;
u32 pixel_rate_csi;
u32 pixel_rate_pixel_array;
};
Members
bus_type
- Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
op_lanes
- Number of operational lanes (input)
vt_lanes
- Number of video timing lanes (input)
csi2
- CSI-2 related parameters
csi2.lanes
- The number of the CSI-2 data lanes (input)
binning_horizontal
- Horizontal binning factor (input)
binning_vertical
- Vertical binning factor (input)
scale_m
- Downscaling factor, M component, [16, max] (input)
scale_n
- Downscaling factor, N component, typically 16 (input)
bits_per_pixel
- Bits per pixel on the output data bus (input)
op_bits_per_lane
- Number of bits per OP lane (input)
flags
- CCS_PLL_FLAG_* (input)
link_freq
- Chosen link frequency (input)
ext_clk_freq_hz
- External clock frequency, i.e. the sensor’s input clock (input)
vt_fr
- Video timing front-end configuration (output)
vt_bk
- Video timing back-end configuration (output)
op_fr
- Operational timing front-end configuration (output)
op_bk
- Operational timing back-end configuration (output)
pixel_rate_csi
- Pixel rate on the output data bus (output)
pixel_rate_pixel_array
- Nominal pixel rate in the sensor’s pixel array (output)
Description
All information required to calculate CCS PLL configuration.
-
struct
ccs_pll_branch_limits_fr
¶ CCS PLL front-end limits
Definition
struct ccs_pll_branch_limits_fr {
u16 min_pre_pll_clk_div;
u16 max_pre_pll_clk_div;
u32 min_pll_ip_clk_freq_hz;
u32 max_pll_ip_clk_freq_hz;
u16 min_pll_multiplier;
u16 max_pll_multiplier;
u32 min_pll_op_clk_freq_hz;
u32 max_pll_op_clk_freq_hz;
};
Members
min_pre_pll_clk_div
- Minimum pre-PLL clock divider
max_pre_pll_clk_div
- Maximum pre-PLL clock divider
min_pll_ip_clk_freq_hz
- Minimum PLL input clock frequency
max_pll_ip_clk_freq_hz
- Maximum PLL input clock frequency
min_pll_multiplier
- Minimum PLL multiplier
max_pll_multiplier
- Maximum PLL multiplier
min_pll_op_clk_freq_hz
- Minimum PLL output clock frequency
max_pll_op_clk_freq_hz
- Maximum PLL output clock frequency
-
struct
ccs_pll_branch_limits_bk
¶ CCS PLL back-end limits
Definition
struct ccs_pll_branch_limits_bk {
u16 min_sys_clk_div;
u16 max_sys_clk_div;
u32 min_sys_clk_freq_hz;
u32 max_sys_clk_freq_hz;
u16 min_pix_clk_div;
u16 max_pix_clk_div;
u32 min_pix_clk_freq_hz;
u32 max_pix_clk_freq_hz;
};
Members
min_sys_clk_div
- Minimum system clock divider
max_sys_clk_div
- Maximum system clock divider
min_sys_clk_freq_hz
- Minimum system clock frequency
max_sys_clk_freq_hz
- Maximum system clock frequency
min_pix_clk_div
- Minimum pixel clock divider
max_pix_clk_div
- Maximum pixel clock divider
min_pix_clk_freq_hz
- Minimum pixel clock frequency
max_pix_clk_freq_hz
- Maximum pixel clock frequency
-
struct
ccs_pll_limits
¶ CCS PLL limits
Definition
struct ccs_pll_limits {
u32 min_ext_clk_freq_hz;
u32 max_ext_clk_freq_hz;
struct ccs_pll_branch_limits_fr vt_fr;
struct ccs_pll_branch_limits_bk vt_bk;
struct ccs_pll_branch_limits_fr op_fr;
struct ccs_pll_branch_limits_bk op_bk;
u32 min_line_length_pck_bin;
u32 min_line_length_pck;
};
Members
min_ext_clk_freq_hz
- Minimum external clock frequency
max_ext_clk_freq_hz
- Maximum external clock frequency
vt_fr
- Video timing front-end limits
vt_bk
- Video timing back-end limits
op_fr
- Operational timing front-end limits
op_bk
- Operational timing back-end limits
min_line_length_pck_bin
- Minimum line length in pixels, with binning
min_line_length_pck
- Minimum line length in pixels without binning
-
int
ccs_pll_calculate
(struct device *dev, const struct ccs_pll_limits *limits, struct ccs_pll *pll)¶ Calculate CCS PLL configuration based on input parameters
Parameters
struct device *dev
- Device pointer, used for printing messages
const struct ccs_pll_limits *limits
- Limits specific to the sensor
struct ccs_pll *pll
- Given PLL configuration
Description
Calculate the CCS PLL configuration based on the limits as well as given device specific, system specific or user configured input data.
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