Switchtec Userspace  PROJECT_NUMBER = 3.1
mrpc.h
1 /*
2  * Microsemi Switchtec(tm) PCIe Management Library
3  * Copyright (c) 2017, Microsemi Corporation
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included
13  * in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  */
24 
25 #ifndef LIBSWITCHTEC_MRPC_H
26 #define LIBSWITCHTEC_MRPC_H
27 
28 #define MRPC_MAX_DATA_LEN 1024
29 
30 enum mrpc_cmd {
31  MRPC_DIAG_PMC_START = 0x0,
32  MRPC_TWI = 0x1,
33  MRPC_VGPIO = 0x2,
34  MRPC_PWM = 0x3,
35  MRPC_DIETEMP = 0x4,
36  MRPC_FWDNLD = 0x5,
37  MRPC_FWLOGRD = 0x6,
38  MRPC_PMON = 0x7,
39  MRPC_PORTLN = 0x8,
40  MRPC_PORTARB = 0x9,
41  MRPC_MCOVRLY = 0xA,
42  MRPC_STACKBIF = 0xB,
43  MRPC_PORTPARTP2P = 0xC,
44  MRPC_DIAG_TLP_INJECT = 0xD,
45  MRPC_RESERVED1 = 0xE,
46  MRPC_DIAG_PORT_EYE = 0xF,
47  MRPC_DIAG_POT_VHIST = 0x10,
48  MRPC_DIAG_PORT_LTSSM_LOG = 0x11,
49  MRPC_DIAG_PORT_TLP_ANL = 0x12,
50  MRPC_DIAG_PORT_LN_ADPT = 0x13,
51  MRPC_SRDS_PCIE_PEAK = 0x14,
52  MRPC_SRDS_EQ_CTRL = 0x15,
53  MRPC_SRDS_LN_TUNING_MODE = 0x16,
54  MRPC_NT_MCG_CAPABLE_CONFIG = 0x17,
55  MRPC_TCH = 0x18,
56  MRPC_ARB = 0x19,
57  MRPC_SMBUS = 0x1A,
58  MRPC_RESET = 0x1B,
59  MRPC_LNKSTAT = 0x1C,
60  MRPC_MULTI_CFG = 0x1D,
61  MRPC_SES = 0x1E,
62  MRPC_RD_FLASH = 0x1F,
63  MRPC_SPI_ECC = 0x20,
64  MRPC_PAT_GEN = 0x21,
65  MRPC_INT_LOOPBACK = 0x22,
66  MRPC_RESERVED2 = 0x24,
67  MRPC_ROUTE_TO_SELF = 0x25,
68  MRPC_REFCLK_S = 0x26,
69  MRPC_SYNTH_EP = 0x27,
70  MRPC_EVENTS_QUERY = 0x28,
71  MRPC_GAS_READ = 0x29,
72  MRPC_AER_GEN = 0x2A,
73  MRPC_PART_INFO = 0x2B,
74  MRPC_PCIE_GEN_1_2_DUMP = 0x2C,
75  MRPC_PCIE_GEN_1_2_TUNE = 0x2D,
76  MRPC_EYE_OBSERVE = 0x2F,
77  MRPC_RCVR_OBJ_DUMP = 0x30,
78  MRPC_RESERVED3 = 0x31,
79  MRPC_PORT_EQ_STATUS = 0x32,
80  MRPC_PORT_EQ_CTRL = 0x33,
81  MRPC_GAS_WRITE = 0x34,
82  MRPC_MRPC_ERR_INJ = 0x35,
83  MRPC_DEV_INFO_GET = 0x36,
84  MRPC_MRPC_PERM_TABLE_GET = 0x37,
85  MRPC_CROSS_HAIR = 0x38,
86  MRPC_RECV_DETECT_STATUS = 0x39,
87  MRPC_EXT_RCVR_OBJ_DUMP = 0x3A,
88  MRPC_LOG_DEF_GET = 0x3B,
89  MRPC_SECURITY_CONFIG_GET_EXT = 0x3C,
90  MRPC_ECHO = 0x41,
91 
92  MRPC_GET_PAX_ID = 0x81,
93  MRPC_TOPO_INFO_DUMP = 0x82,
94  MRPC_GFMS_DB_DUMP = 0x83,
95  MRPC_GFMS_BIND_UNBIND = 0x84,
96  MRPC_DEVICE_MANAGE_CMD = 0x85,
97  MRPC_PORT_CONFIG = 0x88,
98  MRPC_GFMS_EVENT = 0x89,
99  MRPC_PORT_CONTROL = 0x8D,
100  MRPC_EP_RESOURCE_ACCESS = 0x8E,
101  MRPC_EP_TUNNEL_CFG = 0x8F,
102  MRPC_NVME_ADMIN_PASSTHRU = 0x91,
103 
104  MRPC_I2C_TWI_PING = 0x100,
105  MRPC_SECURITY_CONFIG_GET = 0x101,
106  MRPC_SECURITY_CONFIG_SET = 0x102,
107  MRPC_KMSK_ENTRY_SET = 0x103,
108  MRPC_SECURE_STATE_SET = 0x104,
109  MRPC_ACT_IMG_IDX_GET = 0x105,
110  MRPC_ACT_IMG_IDX_SET = 0x106,
111  MRPC_FW_TX = 0x107,
112  MRPC_MAILBOX_GET = 0x108,
113  MRPC_SN_VER_GET = 0x109,
114  MRPC_DBG_UNLOCK = 0x10A,
115  MRPC_BOOTUP_RESUME = 0x10B,
116  MRPC_SECURITY_CONFIG_GET_GEN5 = 0x10C,
117  MRPC_SECURITY_CONFIG_SET_GEN5 = 0x10D,
118 
119  MRPC_MAX_ID = 0x10E,
120 };
121 
122 enum mrpc_bg_status {
123  MRPC_BG_STAT_IDLE = 0,
124  MRPC_BG_STAT_INPROGRESS = 1,
125  MRPC_BG_STAT_DONE = 2,
126  MRPC_BG_STAT_OFFSET = 3,
127  MRPC_BG_STAT_ERROR = 0xFF,
128 };
129 
130 enum mrpc_sub_cmd {
131  MRPC_FWDNLD_GET_STATUS = 0,
132  MRPC_FWDNLD_DOWNLOAD = 1,
133  MRPC_FWDNLD_TOGGLE = 2,
134  MRPC_FWDNLD_BOOT_RO = 4,
135  MRPC_FWDNLD_SET_REDUNDANCY = 5,
136 
137  MRPC_PMON_SETUP_EV_COUNTER = 0,
138  MRPC_PMON_GET_BW_COUNTER = 1,
139  MRPC_PMON_GET_EV_COUNTER = 2,
140  MRPC_PMON_GET_EV_COUNTER_SETUP = 3,
141  MRPC_PMON_SETUP_LAT_COUNTER = 4,
142  MRPC_PMON_GET_LAT_COUNTER_SETUP = 5,
143  MRPC_PMON_GET_LAT_COUNTER = 6,
144  MRPC_PMON_RULE_ERROR_TLP = 8,
145  MRPC_PMON_RULE_TLP_MATCH = 9,
146  MRPC_PMON_RULE_TLP_TO_USP = 10,
147  MRPC_PMON_RULE_TLP_TO_DSP = 11,
148  MRPC_PMON_SET_BW_COUNTER = 12,
149 
150  MRPC_STACKBIF_GET = 0,
151  MRPC_STACKBIF_SET = 1,
152 
153  MRPC_FWLOGRD_RAM = 0,
154  MRPC_FWLOGRD_FLASH = 1,
155  MRPC_FWLOGRD_MEMLOG = 2,
156  MRPC_FWLOGRD_REGS = 3,
157  MRPC_FWLOGRD_SYS_STACK = 4,
158  MRPC_FWLOGRD_THRD_STACK = 5,
159  MRPC_FWLOGRD_THRD = 6,
160  MRPC_FWLOGRD_INVAL = 7,
161  MRPC_FWLOGRD_NVHDR = 10,
162  MRPC_FWLOGRD_RAM_GEN5 = 11,
163  MRPC_FWLOGRD_FLASH_GEN5 = 12,
164  MRPC_FWLOGRD_RAM_WITH_FLAG = 13,
165  MRPC_FWLOGRD_FLASH_WITH_FLAG = 14,
166 
167  MRPC_LOG_DEF_APP = 0,
168  MRPC_LOG_DEF_MAILBOX = 1,
169 
170  MRPC_DIETEMP_SET_CLOCK = 0,
171  MRPC_DIETEMP_SET_MEAS = 1,
172  MRPC_DIETEMP_GET = 2,
173  MRPC_DIETEMP_STOP = 3,
174  MRPC_DIETEMP_GET_GEN4 = 2,
175 
176  MRPC_MULTI_CFG_SUPPORTED = 0,
177  MRPC_MULTI_CFG_COUNT = 1,
178  MRPC_MULTI_CFG_ACTIVE = 2,
179  MRPC_MULTI_CFG_START_ADDR = 3,
180  MRPC_MULTI_CFG_LENGTH = 4,
181 
182  MRPC_PORT_BIND = 0,
183  MRPC_PORT_UNBIND = 1,
184  MRPC_PORT_INFO = 2,
185 
186  MRPC_PART_INFO_GET_ALL_INFO = 0,
187  MRPC_PART_INFO_GET_METADATA = 1,
188  MRPC_PART_INFO_GET_SEEPROM = 2,
189 
190  MRPC_GFMS_BIND = 1,
191  MRPC_GFMS_UNBIND = 2,
192 
193  MRPC_PORT_CONFIG_SET = 0,
194  MRPC_PORT_CONFIG_GET = 1,
195 
196  MRPC_TOPO_INFO_DUMP_START = 1,
197  MRPC_TOPO_INFO_DUMP_STATUS_GET = 2,
198  MRPC_TOPO_INFO_DUMP_DATA_GET = 3,
199  MRPC_TOPO_INFO_DUMP_FINISH = 4,
200  MRPC_TOPO_INFO_DUMP_DATA_GET_GEN5 = 5,
201 
202  MRPC_GFMS_DB_DUMP_FABRIC = 0,
203  MRPC_GFMS_DB_DUMP_PAX_ALL,
204  MRPC_GFMS_DB_DUMP_PAX,
205  MRPC_GFMS_DB_DUMP_HVD,
206  MRPC_GFMS_DB_DUMP_FAB_PORT,
207  MRPC_GFMS_DB_DUMP_EP_PORT,
208  MRPC_GFMS_DB_DUMP_HVD_DETAIL,
209 
210  MRPC_FW_TX_EXEC = 2,
211  MRPC_FW_TX_FLASH = 3,
212  MRPC_FW_TX_TOGGLE = 4,
213 
214  MRPC_DBG_UNLOCK_PKEY = 0,
215  MRPC_DBG_UNLOCK_DATA = 1,
216  MRPC_DBG_UNLOCK_UPDATE = 2,
217 
218  MRPC_KMSK_ENTRY_SET_PKEY = 0,
219  MRPC_KMSK_ENTRY_SET_SIG = 1,
220  MRPC_KMSK_ENTRY_SET_KMSK = 2,
221 
222  MRPC_EP_TUNNEL_ENABLE = 0,
223  MRPC_EP_TUNNEL_DISABLE = 1,
224  MRPC_EP_TUNNEL_STATUS = 2,
225 
226  MRPC_NVME_ADMIN_PASSTHRU_START = 1,
227  MRPC_NVME_ADMIN_PASSTHRU_DATA = 2,
228  MRPC_NVME_ADMIN_PASSTHRU_END = 3,
229 
230  MRPC_PORT_EQ_LOCAL_TX_COEFF_DUMP = 0,
231  MRPC_PORT_EQ_FAR_END_TX_COEFF_DUMP = 1,
232  MRPC_PORT_EQ_FAR_END_TX_EQ_TABLE_DUMP = 2,
233  MRPC_PORT_EQ_LOCAL_TX_FSLF_DUMP = 3,
234  MRPC_PORT_EQ_FAR_END_TX_FSLF_DUMP = 4,
235 
236  MRPC_EXT_RCVR_OBJ_DUMP_RCVR_EXT = 0,
237  MRPC_EXT_RCVR_OBJ_DUMP_RCVR_EXT_PREV = 1,
238  MRPC_EXT_RCVR_OBJ_DUMP_PREV = 2,
239  MRPC_EXT_RCVR_OBJ_DUMP_LOCAL_TX_COEFF_PREV = 3,
240  MRPC_EXT_RCVR_OBJ_DUMP_FAR_END_TX_COEFF_PREV = 4,
241  MRPC_EXT_RCVR_OBJ_DUMP_EQ_TX_TABLE_PREV = 5,
242  MRPC_EXT_RCVR_OBJ_DUMP_LOCAL_TX_FSLF_PREV = 6,
243  MRPC_EXT_RCVR_OBJ_DUMP_FAR_END_TX_FSLF_PREV = 7,
244 
245  MRPC_REFCLK_S_DISABLE = 0,
246  MRPC_REFCLK_S_ENABLE = 1,
247 
248  MRPC_LOOPBACK_GET_INT_LOOPBACK = 2,
249  MRPC_LOOPBACK_SET_INT_LOOPBACK = 3,
250  MRPC_LOOPBACK_SET_LTSSM_LOOPBACK = 4,
251  MRPC_LOOPBACK_GET_LTSSM_LOOPBACK = 5,
252 
253  MRPC_PAT_GEN_GET_GEN = 5,
254  MRPC_PAT_GEN_SET_GEN = 6,
255  MRPC_PAT_GEN_GET_MON = 7,
256  MRPC_PAT_GEN_SET_MON = 8,
257  MRPC_PAT_GEN_INJ_ERR = 9,
258 
259  MRPC_EYE_OBSERVE_START = 0,
260  MRPC_EYE_OBSERVE_FETCH = 1,
261  MRPC_EYE_OBSERVE_CANCEL = 2,
262  MRPC_EYE_OBSERVE_SET_DATA_MODE = 3,
263  MRPC_EYE_OBSERVE_GET_DATA_MODE = 4,
264 
265  MRPC_CROSS_HAIR_ENABLE = 0,
266  MRPC_CROSS_HAIR_DISABLE = 1,
267  MRPC_CROSS_HAIR_GET = 2,
268 };
269 
270 #endif