| Name: | verilator |
|---|---|
| Version: | 3.922 |
| Release: | 1.el7 |
| Architecture: | aarch64 |
| Group: | Unspecified |
| Size: | 9698822 |
| License: | LGPLv3 or Artistic 2.0 |
| RPM: | verilator-3.922-1.el7.aarch64.rpm |
| Source RPM: | verilator-3.922-1.el7.src.rpm |
| Build Date: | Wed May 30 2018 |
| Build Host: | ca-buildarm04.us.oracle.com |
| Vendor: | Oracle America |
| URL: | http://www.veripool.com/verilator.html |
| Summary: | A fast simulator for synthesizable Verilog |
| Description: | Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. |